Using HPC instructions to accelerate DPDK and

In 2020 I wrote a series of white-papers describing using the Intel AVX-512 SIMD
instruction-set (AVX-512) to accelerate packet processing applications. AVX-512
is well known for its ability to accelerate AES cryptography with AVX-512 Vector
AES (vAES) instructions. However, what will be counter intuitive to some, is to
use an instruction-set like AVX-512, that was primarily designed for HPC type
workloads to accelerate networking.

When looking at the kinds of optimizations we were using in DPDK and I
pulled out a number of common threads, and thought to describe them in a series
of papers. In broad strokes, the non-exhaustive list of the kinds of
optimizations that are described are:

All of these optimizations and more are detailed in the white-papers themselves.